1. Field of the Invention
The present invention relates to a process for detecting errors in a serial link of an integrated circuit and to a device for implementation of the process. The invention relates more particularly to a process and device for detecting errors in a serial link of an integrated circuit, or between two integrated circuits, comprising a parallel-serial and serial-parallel port.
The invention is especially applicable when it is desirable to use gigabit-rate serial links having an error rate that is non-null, for example on the order of 10.sup.-15 to 10.sup.-17, to produce an internal link to a logic unit which would normally be produced by a parallel link that is not prone to interference. This substitution is motivated by the fact that high-speed serial links have many advantages. For example, high-speed serial links provide high density and ease of connection with an identical passband, and allow a long link, for example up to 10 meters, which is impossible with standard internal logical links.
2. Description of Related Art
In the case where the serial link is a 1-gigabaud serial link, and assuming that two ports of the same type are communicating with one another through the serial link, allowing machines whose error rate in terms of message corruption and calibration loss and/or protocol inconsistency is on the order of 10.sup.-17 to communicate with one another, it will be noted, taking into account the speed of the serial link and the error rate of the machine, that this seemingly low error rate can generate a substantial error and an abnormal operation of the machine every two days.
Integrated circuits comprising interfaces between a parallel bus and a serial bus are known, but in general they do not comprise a device and process for detecting and recovering from errors, since they are based on the principle that the communication does not include any errors involving the serial link, or if it does include any, the detections of errors and recoveries from errors are handled in a higher layer (calibration loss) at the software level.